Eurocircuits and conflict minerals

What are conflict minerals?



Conflict minerals are minerals originating from areas of armed conflict and human rights abuse, notably in the eastern provinces of the Democratic Republic of the Congo.

These minerals are traded through middlemen from neighbouring countries, so countries where conflict materials can originate from include also Angola, Burundi, Central African Republic, Congo Republic, Rwanda, Sudan, Tanzania, Uganda, and Zambia.



The most commonly mined minerals are cassiterite, wolframite,coltan, and gold, which are extracted from the Eastern Congo,  We are concerned about cassiterite (basis for making tin) and gold, as these metals are used in our production process.


We contacted our suppliers for these metals and got confirmation that the material we receive from them do not origin from conflict areas. Based on this information we can issue a conflict minerals declaration.

Supporting documents :

Eurocircuits conflict minerals declaration   conflict minerals declaration.pdf

Felder conflict minerals declaration (supplier of tin for HAL)   felder konflikt-metalle.pdf

Confirmation Safina ( supplier of gold)  safina.pdf

Confirmation Ampere (tin for plating line) ampere.pdf

Gold plating for edge connectors

Gold plating over edge connectors

Eurocircuits offer two types of gold finish: Electroless Nickel Immersion Gold (ENIG) as a surface finish for the whole PCB, and hard plated gold over plated nickel for edge-connector fingers. Electroless gold gives excellent solderability, but the chemical deposition process means that it is too soft and too thin to withstand repeated abrasion. Electroplated gold is thicker and harder making it ideal for edge-connector contacts for PCBs which will be repeatedly plugged in and removed.

goldplated edge connector



We plate the hard gold onto the PCBs after the soldermask process and before we apply the surface finish to the rest of the board. Hard-gold plating is compatible with all the other surface finishes we offer.

edge connector


We first plate 3 – 6 microns of nickel onto the edge connector fingers and then on top of that 1 – 2 microns of hard gold. The plated gold is not 100% pure; it contains some cobalt to increase the wear-resistance of the surface.

We normally bevel the edge connectors to ensure easy insertion. Bevelling can be specified in the order details.

edge connector profile


To make sure that the gold fingers align exactly with the edge-connector profile, we rout the vertical edges of the connector on the first drill run. The edges of the connector are then exactly aligned to the printed image.

In some cases one or more gold fingers are shorter than the rest, so that the longer pads connect first when the PCB inserted into the connector. This means that the shorter pads cannot be connected vertically to the plating bar. They have to make the connection needed for electroplating in another direction (see illustration. Here the blue lines represent the profile added at first drill stage and the green the final profiling).

edge connector schematic.png


After plating we check the adhesion of the plated nickel and gold with an industry-standard tape-test. We measure the thickness of the plated layers with a non-destructive X-ray measuring machine.

Limitations of the technology

    • The plated pads have to be on the edge of the PCB, as this is an electroplating process. There has to be an electrical connection between the plated pads and the production panel frame.
    • The maximum length of the plated pads is 40 mm as we use a standard shallow plating bath .
    • Inner layers have to be free of copper at the edge of PCB. Otherwise the bevelling could expose the copper.
    • If you want your PCBs delivered in a customer panel, the panel frame/border must be open on the edge connector side to allow us to make the connection for electroplating.
    • We can plate hard gold on two sides of PCB. But if the connectors are on the opposite sides of the PCB there has to be a minimum 150 mm between them.

edge connector both sides.jpg
  • To ensure optimum quality surface-finish, do not place any plated holes (PTH), SMD or other pads closer than 2.00 mm (80 mil) to the gold fingers – see drawing.
    edge connector dimensions.png


Eurocircuits production data – what’s in it?

To produce your board we use your design data in Gerber or EAGLE format and first perform the necessary front end actions as described in our white paper: “What do PCB fabricators do with your data before they make your PCBs?“.

When this is done and your board is ready for production, we save your board’s production data in your account.  This data we call the job’s “single image” data.  “Single image” means the data we load onto our order-pooling production multi-panels, so it may refer to a single circuit image or to a delivery panel if this is what you have ordered. This is the data that is visualized in the PCB image.  You can download the full set from within your customer account.

visualisation customer account

The download of the single image production data from the Eurocircuits site has been possible since we launched our e-business platform more than 10 years ago. This open business policy has convinced customers over the years to come to us for their prototypes and small series even if they planned to have their large series produced in the Far East. We offer a fast and convenient way to calculate prices and place orders, a thorough data verification and manufacturability analysis and highly professional production processes.  Combine this with the possibility to download the verified data and use it for production wherever else you want, and you have the best possible start for the life cycle of your products.

The single image files are name coded by Eurocircuits. But this is no secret either. Let us explain what the files are and what their names stand for.

file name convention.docx

file name convention

The format of the files is mainly DPF.  This is the internal format for UCAM, the front-end data preparation or CAM (Computer Aided Manufacturing) system we use designed and developed by Ucamco.  The paste files can also be downloaded as Gerber data.  To read DPF files as well as Gerber data and Excellon drill files we recommend GC-Prevue, available as a free download from

We are sometimes asked if it possible to reload the single image data back into a CAD system.  This is totally dependent on the CAD system.  We have only input and processed manufacturing data.  Other PCB manufacturers can use it for production through their own CAM systems.  However the manufacturing data doesn’t contain any component information like foot-print coordinates or a functional net-list where nets are linked to component pin numbers and are described as power, ground, data line, etc… A successful reload of DPF or Gerber production data into a CAD system depends entirely on the functionality available in the CAD-system and should be investigated there.

Our team will gladly answer any queries you may have. Contact us on .

Soldermask on via-holes in case of chemical Nickel-Gold surface finish

Soldermask on via holes

There are 3 ways our customers prepare their layouts with respect to covering via-holes with soldermask:

  • Vias open (not covered by soldermask) on both sides of the PCB




  •  Vias closed (covered with soldermask) on both sides of the PCB


via covered


  • Vias open from one side and covered from the other side of the PCB
via half open

As necessary background information we need to briefly introduce you into the technology of applying soldermask to the boards.

First we cover the whole surface of the production panel with soldermask ink and then dry the panel (printing the soldermask)

The ink we use is a UV sensitive material. When exposed to UV-light, the ink will harden (exposing  the soldermask)

Ink that is not exposed remains soft and can be washed away using a 1% alkalic solution (developing the soldermask)

The easiest production method is to have all vias open from both sides. The vias will be clean. They will not contain any contamination nor soldermask. The next picture shows vias free of soldermask. We did not expose the soldermask on the via pads so that it remains soft and is washed away during the developing process.

via free picture

Another practical production method is where the vias are covered on both sides of the PCB. We expose the soldermask on both sides of the via-pad and via-hole so it will harden and stay on the via-pad and over the via-hole to close it. There is a risk however that (mostly in case of via-holes with a larger diameter) the via-hole is not completely covered and a small opening remains in the middle.

via partially plugged

There is a danger that chemicals get stuck in these small openings during the processes that follow after the soldermask application. These chemical can contaminate and affect for instance the chemical Ni/Au process. A further danger exists that chemicals of the Ni/Au process remain in these openings and as they are agressive chemicals they might keep on reacting in the via hole years after the board has been produced causing possible failures in usage of the PCB in its application.

discolored pad

The third case (vias covered from one side and open from the other side of the PCB) is the most problematic in production. This design creates a pocket. We expose the soldermask from one side but not from the other side. This soldermask in the middle of the via-hole will only be half polymerised. During the baking process this material can come out of the hole from the open side and contaminate the copper surface and thus disturb the surface finishing process. The pictures below shows a typical failure.

gold contaminated


Vias and Chemical Nickel-Gold (ENIG)

Vias that are not completely covered or not properly filled with soldermask may create “skip pads” in the ENIG process.

discolored pad discolored pad

Till now we didn”t receive any reasonable explanation from our material suppliers nor did we found one elsewhere that reveals the source of this problem. However supplier advise and long term experience guide us to two possible solutions to avoid the issue:

Modify the layout so that all vias are open. Our engineers favour this solution. Sadly this is not always accepted by our customers or the design may not allow it.

Apply the soldermask after the ENIG process. This is a costly solution as all copper surfaces are gold-plated and the soldermask adhesion becomes worse.

For closed via-holes we have developed an alternative solution which avoids chemicals getting trapped in the partially closed via-holes during developing of the soldermask or during application of the Ni/Au. Before the coating the entire panel with soldermask we selectively print soldermask into the via holes using a stencil. During a second print run we then cover the whole panel. This way the via-holes are completely filled with soldermask. An even layer of soldermask now covers the via-holes leaving no pockets to hold residual chemicals. We have used this technique for over 6 months, and it has proved successful in dramatically reducing the number of skip pad problems.

The following movies show this process of via filling and soldermask printing.

Setting up the machine:

Printing the soldermask into the via holes:

Result after filling the via holes:

via filled

Cover the panel with soldermask:

Result after printing the soldermask:

via covered


Drying the soldermask layer:

Eyes on the future, feet on the ground – Technology seminar by ACB

On April 25, ACB organized their technology seminar….Eyes on the future, feet on the ground…

ACB, known in Europe as leading manufacturer of High Technology & Quick Turnaround Printed Circuit Boards, organized its first technology seminar.

The brand new CEOGilles Rigon, opened he seminar with explaining all about the ACB philosophy.   “S” for simple and easy solutions where possible, “S” for souple and flexible processes and “S” for Solid and reliable processes and how they balance their “eyes on the future” with their “feet on the ground” approach.  In fact, the importance of this balance would return in many lectures coming.

Arnaud GrivonPCB/PCBA Technology expert from Thales showed us the possibilities and limits from stacked filled microvias and how design has a major impact on their reliability.   This technology is required to make routing possible for fine pitch BGA or array components (pitch < 0.5 mm) using microvia-in-pad and filled stacked vias.  The Cu filling is not only creating a smooth surface for assembly but can increase the reliability of the microvia too, as long as it is properly filled.  Tests have proven that the aspect ratio is max 0.8.  This means that microvias can only be filled completely in a thin insulation-layer. This sounds logic but this technology is highly sensitive and requires strict process control.

arnaud grivon – thales 

This brings us to the following presentation.  Wim Perdu, CTO at ACB, spoke about the sense and nonsense of IPC requirements in design, process and inspection.  For high density boards and fine pitch design, the feasibility of some requirements in IPC class 3 or class 3A is doubtful and not always relevant for better or more reliable quality, and the cost related with the required inspections is hallucinatory.  He expressed what many of us think but don’t dare to say because we don’t want to awake sleeping dogs.  Instead of attacking IPC standards, we try to set up workable methods to control our processes.  We set up mechanisms to avoid failures instead of detecting them in a final product.  And, indeed it is more important to know the capabilities of your supplier then to “overspecify” the products, since many aspects are hardly possible to inspect in a finished product and like Wim said: The reality is simple: if it is offered for free, it is not done.

wim perdu-acb

The next presentation came from Jan Vanfleteren who is developing for IMEC- UGent/CMST flexible and stretchable circuits.  There is an increasing demand for portable, wearable and implantable electronics and sensor systems.  To achieve the needs for comfort, place and weight saving CMST developed a technology to integrate flexible ultra thin chip packages in stretchable circuits which are completely embedded in order to make them washable and implantable.  This technology tries to make use of the existing standard PCB processes and uses temporary layers for support during processing.  These support layers are removed later on and the result is complete embedding in elastic materials.  Although this is an example of the “eyes on the future” aspect, we saw more than 1 realization of stretchable, dynamically deformable or integration in textile.  The challenge now is to have these products developed and produced on an industrial scale.

Back to the essence now:  Wim Huwel, NPI Engineer at ACB, convinced the attendees about the importance of the DFM (design for manufacturing).  It implies an early cooperation between designer and PCB manufacturer.  It combines tools and techniques to achieve better quality in a shorter development time and a more mature product at a lower cost.  Early involvement makes it possible to guide designers to use the correct industrial design rules and chose the best material for their application.  It also avoids creating the need of extra ordinary process capabilities.  Use the design rules and keep it as simple as possible.  He showed us many examples of how almost impossible build-ups were altered to the ACB “standard constructions”
= > For this reason, we, at Eurocircuits send out all these (sometimes annoying) remarks and exceptions.  We share the same opinion: use the design guide lines, check the classification table and keep it simple!

Geert Willems, driving force behind the EDM-projects, at his turn continued with an exposé about via reliability.  Too difficult to follow for most of us but he showed the need of physical models to understand the parameters that influence the reliability of vias such as via diameter, PCB thickness, the CTEz of the material and the Cu deposit with their degree of importance.  He announced that all conclusions will be included in the new DfM Guideline coming soon.
=> As EDM-partner of the early hour Eurocircuits sat down with Geert on this subject some years ago. Based upon his reliability model, we defined the basic material parameters for the base material used in our pooling services. This lead to a better quality of lead free boards and zero material defects during the last 3 years.

Wim Christiaens, NPI Engineer at ACB, returned to the subject of stacked and filled micro-vias and the importance of well filling. He guided us through the challenges of the projects they set up to achieve this properly filled micro-via. He used different BGA configurations to explain the use and the importance of the µBGA design rule table and the relation with the PCB class.  If you ever have the need for this technology, you should consider his involvement at an early stage.  His explanation of this rather difficult subject was very clear!

The row of presentations was closed with a lecture from Johan De Baets, from IMEC-CMST about Embedded components in printed circuit boards.  Traditional printed circuit boards have components on top and/or bottom.  Embedded technology started around 1990 with printed resistors and capacitors to arrive at the current stage where silicon and chip become embedded in the PCB. During the last 15 years several methods were developed to embed active components too.  Johan introduced the HERMES project: High density integration by Embedded chips for Reduced size and Electronic Systems. To be able to combine and optimize all the available existing technology from design, PCB, PBA and silicon dies many industrial players are working together in this project.  It requires a complete new business model to make this project possible.

The event was held in the Verbeke foundations residence and proved to be a perfect location for contemporary art and technology crossover.

acb event verbeke foundation

Large boards and pooling

Large boards and pooling – new guidelines 

 425×425 top view


Over the last 12 months we have received an increasing number of boards in our pooling services at the maximum size allowed 425 x 425 mm.  These are not genuine single circuits but panels made up of many smaller circuits.  To get around our specified maximum panel size 350 x 250 mm, the individual circuits on these oversize panels are not profiled out.  In that way the users can describe the panel as a single circuit, though we know, of course, that they will subsequently cut out the individual circuits.







This practice raises two serious issues. 

First it impacts on the overall efficiency of the pooling service.

To keep prices down for all our customers we need to use as much of each pooling panel as possible. The more customers’ orders we can produce for a given area of material, the lower can we make our prices.  But a panel 425 x 425 mm means that the rest of the pooling panel is wasted.  That’s one reason why we set the maximum customer panel size at 350 x 250 mm (the other is that this is also the largest standard size panel used on many or most automatic assembly machines).  We allowed a maximum circuit dimension of 425 mm to give maximum flexibility to our customers, knowing that very few actually need individual circuits 425 x 425 mm.

Second, it is likely to produce less good PCBs.

Putting together panels with several different circuits on them requires skill and experience to optimise tooling and to achieve a good copper balance on each side and side to side.  We use sophisticated software to calculate the plating index which measures how well the copper is balanced.  When we apply this to these large  combination panels, in most cases we see a very poor copper balance with significant areas of over- and under-plating, reducing the quality of the finished circuits.

425×425 bottom plating 425×425 top plating2 425×425 bottom plating 2 425×425 top plating

To avoid these issues we have decided to set the maximum size of a single circuit on our pooling services at 8.75 dm2, the same area as our largest eC-registration-compatible panel 350 x 250 mm.  You can order larger boards up to a maximum in one dimension of 425 mm, (e.g. 425 x 100 mm) so long as the total area is not more than 8.75 dm2.The largest panel size on the pooling services remains 350 x 250 mm whether panelised by Eurocircuits or by the customer.  Further it is our policy that all customer panels prepared by us according to the Eurocircuits panel rules are eC-registration-compatible (maximum 350 x 250 mm to fit the eC-equipment).

If you need a single circuit larger than 8.75 dm2 or a panel larger than 350 x 250 mm, then upload it as an inquiry in On demand.  We will check that it is falls within the parameters of good production practice.  If it does, we will send you a quotation.  If not, we will make suggestions to improve its manufacturability.

Which surface finish fits your design

Surface Finishes on printed circuit boards

Then finally, you have finished your design and the moment has come to order the PCB.  You have considered all the important aspects. The DRC check is done and you are relieved: no errors remaining.

The online calculator shows you the default pooling options and offers you the possibility to adjust some of them to your specific need.  En there you bump onto the Surface Finish.  What is Surface Finish and how to make the right choice?

treatment – surface finish

Since all finishes have advantages and disadvantages, it is important to stand still by their application and to check how your boards will be treated during assembly.   The different finishes we offer are Lead-free HAL, Electroless Nickel/Immersion Gold (known as ENIG) and Immersion Silver (ImAg).  All of these are Lead-free and can be used for a RoHS design but also in a SnPb assembly.  Edge connectors can be covered with hard Gold (electroplated Ni/Au).


The use of HAL as a finish results in PCBs with the highest level of solderability and solderability robustness with regards to multi-step assembly and storage and all this for a reasonable price.  On the other hand, the HAL process requires the submerging of the complete PCB in liquid solder and is responsible for extra thermal load on the PCB.  For that reason, it isn’t the best choice if your board requires small via holes or the board exceeds a normal thickness (when the aspect ratio is high).  Another aspect is the less flat surface it may create.  Although we try to achieve a flat surface, the variety of the amount of solder present on the solder-pads can make this finish less suitable for small sized components with small pad sizes.

ENIG (chem. Ni/Au)

Many customers choose this finish because of the flat surface, the good solderability and the acceptable shelf live, but also because they are already familiar with this finish from before the introduction of the Lead-free assembly.  At least, this parameter could remain unchanged and gave at that time some confidence.  However, the ENIG process is a complicated one with a higher risk of defects (skip plating, black pad or interface embrittlement).  When using ENIG, the solder-joint is formed between the solder and the Ni layer of the NiAu surface, not with the underlying Cu.  The Au is completely dissolved in the solder-joint. This interface is considerably more brittle than a SnCu interface and therefore not recommended for applications where shock, bending or strong vibrations are part of the picture. And last, but not least: it is the most expensive surface finish of the list.  For some applications, like key pads or wire bonding, it is the better choice.

Immersion Silver (chem. Ag)

This surface finish is often a bone of contention, some love this finish, and some hate it. It offers a flat surface, a very good solderability and a long shelf life.  The solder-joint is created with the underlying Cu, since the Ag is dissolved during soldering.  Sounds good, but the ImAg is susceptible to sulferdioxide (SO²) which tarnishes the surface and creates the AgS² layer.  This layer affects adversely the surface solderability. To avoid this tarnish, we pack the PCBs in silver saving paper and require hermetic sealing to avoid moisture and atmosphere SO² coming in.  In case of multi step assembly, the partially assembled boards should better be stored in a sulfur-free atmosphere. If all this handling is not a problem and taken into account, it is the best choice and… the cheapest.

Any lead free

If you don’t choose a finish, your board will be produced on a production panel where the finish is lead-free HAL or chem. Ag or chem. NiAu.  The choice is defined by other PCBs appearing on the same panel.

Gold for edge connectors

Due to the need of abrasive resistance of edge connectors we can finish these connectors with a layer of electroplated NiAu (hard gold).  This finish is processed in a special sized bath construction and only used for these connectors.  It is not possible to have this hard gold processed on other locations of the PCB.


Carbon combines a high mechanical strength with a good electrical conductivity and can often be used as a substitute for gold on contacts.  It is applied directly on the Cu and used for switch contacts, foil keyboards and can enable the creation of cross-over conductors.  It is resistant to HAL and soldering processes without showing practically any change in resistance.  Carbon is printed (conductive ink) and the accuracy in position and image is therefore limited by the printing process.

Summary table

eurocircuits surface finish.jpg


Bow and Twist in printed circuits

What is Bow and Twist?

According to the IPC-A-600 standard bow and twist (flatness of the board) is :

“Flatness of printed boards is determined by two characteristics of the product; these are known as bow and twist. The bow condition is characterized by a roughly cylindrical or spherical curvature of the board while its four corners are in the same plane. Twist is the board deformation parallel to the diagonal of the board such that one corner is not in the same plane to the other three. Circular or elliptical boards must be evaluated at the highest point of vertical displacement. Bow and twist may be influenced by the board design as different circuit configurations or layer construction of multilayer printed boards can result in different stress or stress relief conditions. Board thickness and material properties are other factors that influence the resulting board flatness.”

Why is the flatness of a printed circuit board important?

  • During the production of the board the flatness of the panels is important for handling and for positioning the panels on the machines
  • During the assembly process the flatness of the panels is important for correct solder paste deposition and component mounting
  • Flatness is an aspect of the visual quality appearance of the boards.

What are the acceptability criteria for bow and twist?

  • For all boards the bow and twist should be 1.5 % or less
  • For boards using SMD components ( the majority of the boards) the bow and twist shall be 0.75% or less.

How to measure the bow and twist?

The IPC-TM-650 test methods manual describes the method to calculate bow and twist percentages

What can the PCB designer do to avoid bow and twist?



  • Create a symmetrical copper distribution. As far as possible aim for an even copper distribution across each layer.  For multilayers as far as possible arrange signal and plane layers symmetrically around the centre of the PCB.  If there are areas of very low copper density and areas of high density or full copper it”s a good idea to add copper to the low density areas to balance out the copper distribution.
  • Select a symmetrical build-up of cores, pre-pregs and copper thicknesses.

What can a PCB producer do to avoid bow and twist?

  • Select base materials that are suitable for lead-free soldering. We use for instance IS400 from Isola or NP155 from Nanya
  • Use proper pressing parameters for multilayers to reduce stress in the final PCB
  • Do not mix materials from different types or vendors, and lay up the material warp and weft correctly
  • Use horizontal ovens for the curing processes
  • Cool down the panels on a horizontal surface (for instance after hot-air solder-levelling)

What can an assembly house do to avoid bow and twist?

  • Avoid heavy thermal shock during the soldering process by using a suitable soldering profile
  • Organise adequate support during the soldering process.

Your opinion?

Even if the pcb producer and assembly house take the necessary care to avoid bow and twist the deciding factor is the design of the board.
We have been brainstorming at Eurocircuits recently to see if we can develop a tool for electronics designers to predict the risk of bow and twist. This could be in the form of an index or a visual tool in the same way as our latest plating simulation tool .
As we cannot judge how useful this is for electronics developers, we ask you to comment on this post with your opinion. If there is a genuine interest in such a tool, we will (try to) develop it. You can also give your opinion on the plating simulation tool, and suggest to us how we can improve it , Or just give your opinion in our poll below

Elsyca Intellitool Matrix plating project

Elsyca Intellitool Matrix plating project

Eurocircuits”role in the project sets a new competitive standard

Making efficient pooling panels belongs to the core business of Eurocircuits. It is a necessity to ensure cost-effective production of prototypes or small batches. 
Eurocircuits started as a trader of printed circuit boards in 1991. Soon after, in 1993 we got involved in production. It has been our aim from the start to use pooling techniques for a number of reasons :

  • Save cost by increasing production efficiency
  • Save the environment by reducing waste

The idea of making pooling panels was not new in 1993. On the Benelux market a dutch company was already successfully offering single sided boards in pooling since the eighties of the last century. For double sided boards however it was not that common yet.

When we introduced combination panels for double sided boards in our own production in Hungary there was a lot of resistance from the operators and from the production management. They saw the complexity of their job increase, and technological challenges had to be taken care of.

Now, almost 20 years later, most technology issues have been taken care of, except for one major area, the galvanic copper plating.

For this galvanic process, the design of the PCB plays a vital role in the outcome of the process. In pooling panels there is even an influence of the design of one board on the copper deposition on surrounding designs. That means that we have to be very careful how to build our panel layouts.

The restrictions in panel configuration create limitations that affect the efficiency in our production. As a producer you can look at this problem in two ways:

  • Focus on efficiency and accept uneven copper distribution. Also accept that the quality of the PCB”s produced for one customer can be influenced by the design of another pcb on the same pooling panel.
  • Focus on quality – stick to an even distribution and minimum copper plating thickness all over the panel. Accept that part of the panel surface gets lost because of extra copper areas and spacing introduced to balance out the galvanic layer. Also accept that not all jobs can be pooled with acceptable plating results.

Eurocircuits decided not to take any plating quality risks. We accepted the restrictions dictated by the plating process for a long time.The Elsyca Intellitool matrix copper plating is going to remove these restrictions. 

Project partners :

Elsyca NV, Wijgmaal – Belgium
MacDermid Germany

Elsyca Intellitool plating – the concept

Elsyca Intellitool is a software controlled electroplating tooling concept developed by Elsyca. It reduces the pattern dependence of the deposited layer of copper on the boards. The main change from a standard plating cell is the introduction of a controllable grid ( matrix) of anode segments, at a small distance of the board to be plated.

The concept consists of 3 parts :

  • 1.A simulation and optimisation tool which is a further development of Elsyca Smartplate, a software we use at Eurocircuits to simulate the plating process and to decide if a pooling panel is fit for production or not. The simulation tool optimizes the current on each anode segment in time to yield the desired plating thickness and uniformity on the board. The simulations counts with parameters like properties of the plating tank, design of the pcb, resisitivity of the substrate. The result of the optimization is sent to the control unit to feed the matrix.
  • 2.The matrix feeder contains a microprocessor that reads the calculated pattern of the current, and controls a matrix of digital to anode converters (DACs). This imposes the correct current on each anode segment ( pin). An amplification of the current can be implemented.
  • 3.The anode matrix, mounted on a printed circuit board. Each anode pin is connected to the matrix feeder.

Intellitool concept picture

Elsyca Intellitool is organising the anodes as a matrix with the same size as the panel to be plated, and every point in the matrix can plate with a different current. All individual currents can be controlled in time and intensity.This way the current density is not spread evenly over the panel, but is adjusted to the differences in copper distribution in  the pcb design. This can be useful to balance differences in copper distribution within a single board, but gets even more interesting when there are different designs combined on one panel ( pooling-panel).

More information about the Elsyca Intellitool concept is available on their website

Elsyca Intellitool – in practice.

Eurocircuits is using the software from Elsyca to simulate plating (Smartplate) and judge the plating feasabilty  of its pooling panels. Intellitool is going to take us a step further. We are not going to use the software just for making a judgment. The results of the simulations will be used to control the plating process by instructing each of the anodes in the matrix on the current to be used and the time to be plated.

The Elsyca Smartplate CAM output is sent directly from our UCAM Cam system to the plating line to control the process. Operator influence on the process will be eliminated.

Our plating process will be integrated in our production processes in a similar way as is now the case for CNC machines, test equipment, etc.

Elsyca Intellitool – labo test

To test the concept Elsyca made a labo plating setup. You can read an abstract of the concept and the labo test results

Elsyca Intellitool – testing in a production environment

Eurocircuits and Elsyca are testing the Elsyca Intellitool concept in a purpose built galvanic cell in our production site Eurocircuits Aachen Gmbh in Baesweiler, Germany.

The galvanic cell is built to treat one standard size Eurocircuits pooling panel ( 530 x 460 mm ) The PCB pattern on the pooling panel will vary from one production run to another.

Intellitool test cell

The cell contains two anode arrays ( one for the front side, one for the backside of the pcb panel)

Intellitool matrix

The tank is filled with MacDermid specialised chemicals for electroplating printed circuit boards, and the Eurocircuits pooling panel is precisely positioned between the two anode arrays.

Intellitool with panel positioned

Testing the Elsyca Intellitool production cell  – November 17-2011

On November 17 tests with production panels taken out of regular production batches in Eurocircuits Aachen were plated in both our conventional plating line and in the Intellitool testcell.

Trials were conducted to evaluate the Intellitool concept as follows :

1. Test to improve the copper distribution on the panel against the conventional line :

  • Intellitool panel : Plating thickness (in holes ) between 33 and 53 micron
  • Conventional panel : Plating thickness  (in holes) between 29 and 62 micron
  • The use of Elsyca Intellitool reduces the plating spread with 50%
  • Intellitool test 1

2. Test to speed up the plating process  with similar copper distribution as in the conventional line


  • Intellitool panel : plating time 40 minutes
  • Conventional panel : plating time  70 minutes
  • The use of Elsyca Intellitool reduces the plating time with more than 40% while maintaining the same plating spread.
  • Intellitool test 2
More tests are planned to further optimize the Elsyca Intellitool product. As a lead customer this will be performed in close collaboration between Elsyca and Eurocircuits.  By the end of February 2012 we will build a new galvanic line in our production unit in Eger, Hungary to test the Elsyca Intellitool in an automated production line.

Through hole component soldering with the eC-reflow mate

PIP (Pin in Paste) technology for soldering trough hole components

PIP is a technology for assembling through hole components using a conventional reflow soldering process. The process is also known as THTR (Trough Hole Technology Reflow).

Most PCB”s that contain SMD components usually also contain some through hole components, such as connectors, switches, capacitors and so on . The principle of PIP is that through hole components are placed into PTH holes with SMT solder past and then reflow soldered with the other SMT components together.

We judge this can be a technology of interest for electronics developers that decide to assemble their prototypes themselves.

The next figure shows the process sequence we advise :

Important parameters for this process are hole and pin sizes, boards thickness, thickness and opening of the stencil , used paste printing technique and used paste.

It is obvious that only components that can withstand the reflow soldering temperatures can be soldered this way.

Most datasheets for PIP connectors also contain useful infomation such as the recommended stencil design.

Some hints based on our experience to give you the best results:



  • Reduce the hole size as small as possible for the component pin to be soldered
  • Avoid big annular rings
  • Do not put via holes in areas where solderpaste needs to be printed
  • Position the squeegee at an angle of 45° to the stencil to improve the pressure of the paste
  • Increase the size of stencil apertures to overlap on the area around the pth hole (overprint) – when the solder paste melts, it will flow into the holes.

Image of the bare bottom side of the pcb after printing the solderpaste on the top side :

Cross-section of the component pin after soldering with PIP technology :

Advantages of the PIP technology

  • You can spare one step in the assembly process, this reduces cost as well as time.
  • All components are processed within one SMT solder process.
  • Good wetting and less risk for solder bridges
  • Connectors suitable for PIP generally require less board space, and are easier to repair then SMT connectors.

The Pin in Paste technology is very useful, because you can save time and manpower. We think this technology makes it easier for electronics developers to assemble prototypes in-house in a reliable, quick and affordable way.

More information about the equipment used in the test is available in our section on SMD reflow equipment